1. Field of the Invention
The present invention relates to a fabrication technique for semiconductor integrated circuits, and more specifically to the process needed to obtain the alignment marks necessitated by the use of specific photolithographic exposure tools.
2. Description of Prior Art
The trend in the semiconductor chip industry has been to produce faster devices at reduced costs. The ability of the industry to meet these objectives has been influenced in part by the success of the industry to fabricate smaller chips, exhibiting improved performance due to the decreased delay times, and lower costs, arising from the ability of placing more of these smaller chips on a wafer. The reduction in chip size, accomplished via reductions in specific chip image dimensions, has been realized by the rapid advances in the photo lithographic discipline. Improvements in exposure cameras, as well as developments enabling the use of more sensitive photoresist materials, have allowed smaller chip images to be obtained, thus reducing chip size and increasing circuit density. However placing more devices on a chip reduces the chances of sustaining, or improving the chip yield, due to the increased active device area on a specific chip. Therefore the semiconductor industry has also concentrated on methods needed to increase chip yield.
The objective of improving chip yield has been addressed in basically two manners. First the fabrication disciplines, such as low pressure chemical vapor deposition, (LPCVD), ion implantation, (I/I), etc, have created better processes and equipment which add less defects to the chip fabrication process. The ability of these disciplines to avoid contamination, the in process wafer, via particle contamination, etc, has allowed higher yields to be realized. Secondly, device engineers have created fabrication techniques which minimize the creation of silicon damage, during the fabrication process. For example, high energy, high dose, ion implantation processes, can leave damaged regions in silicon, thus creating areas of device vulnerability and subsequent yield loss. For this case processes have been developed in which the relationships between defect generation and implant conditions are understood, and thus deleterious conditions are avoided, or anneal cycles have been added at the conclusion of the implant cycle, to relax the damage.
Another defect mode, due to silicon damage, is the health of the silicon wafer, prior to the initial processing sequences. Silicon wafers, obtained from crystals grown by the Czochralski method, can exhibit supersaturated interstitial oxygen, which in turn can percipitate at the wafer surface during routine fabrication processes at temperatures in the range of about 900.degree. C. These percipitates may grow large enough at the wafer surface to result in crystal defects, dislocation loops, etc, thus interfering with normal device functioning, thus resulting in ultimate yield loss. Methods have been developed in which the starting wafer is subjected to a series of heat cycles, in an attempt to remove oxygen from an area of the wafer where the devices are to be fabricated. This area is known as the denuded zone, that is an area in which the deleterious oxygen has been reduced or removed, and the ability to produce high yielding devices is increased. Hirao, etal, in U.S. Pat. No. 4,661,166, describe a process in which a series of heat treatments are used to produce a denuded zone near the wafer surface. In addition this invention offers the advantage of creating another zone, below the denuded zone, which consists of a silicon structure that acts as gettering sites for other impurities, such as metals, etc, which can also degrade device yield if left to diffuse to the wafer surface.
These processes used to initially create a denuded zone in the starting wafer, although successful in reducing defect related yield loss, are costly. A method will now be described in which a process sequence is invented in which the denuded zone will be created during the ongoing process. This fabrication sequence will use no additional steps, and thus cost reductions, as well as increased chip yields, due to defect free denuded zones, will be realized. The major direction used in this invention will be to avoid any process temperature step, that will lead to oxygen percipitate formation at the wafer surface, prior to formation of the denuded zone. Thus prior to creating the denuded zone, during a 1100.degree.-1200.degree. C. cycle, all insulator layers will be obtained via low temperature chemical vapor deposition processes.